DSP FPGA Design Using Xilinx System Generator

4k+ rating

  • 10 hr 07 min
  • 67 lectures
  • Overview
  • Curriculum
  • Testimonials


This course allows you to explore the System Generator tool and gain the expertise you need to develop advanced, low-cost Digital Signal Processing designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

Who Should Attend?

System engineers, system designers, logic designers and experienced hardware engineers interested in DSP design training who are implementing DSP algorithms using the MathWorks MATLABĀ® and SimulinkĀ® software and want to use Xilinx System Generator for DSP design.


  • Experience with MATLAB and Simulink software.
  • Basic understanding of signal processing theory.

Skills Gained

  • Describe the System Generator design flow for implementing DSP functions
  • Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation
  • List various low-level and high-level functional blocks available in System Generator
  • Run hardware co-simulation
  • Identify the high-level blocks available for FIR and FFT designs
  • Implement multi-rate systems in System Generator
  • Integrate System Generator models into the Vivado IDE
  • Design a processor-controllable interface using System Generator for DSP
  • Generate IPs from C-based design sources for use in the System Generator environment

  • arithmetic Operations

    Fixed Point Format-Signed and Unsigned (with or without binary point), Gateway In & Out, Saturation and Wrap in fixed-point numbers, Applications of Round and Truncate in fixed point while arithmetic operations, Hardware Cost of Saturation, Wrap, Round and Truncation, Addition, Subtraction, Multiplication, Division, Scaling and Shifting, Complex arithmetic- Complex multiplication, conjugate etc.

    3 months min


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  • Course Name
    DSP FPGA Design Using Xilinx System Generator
  • Upcoming Batch
    23 July 2022
  • Coures Duration
  • Batch Size
  • Class Time (Weekends)
    09:00 pm to 11:00 pm
  • Class Time (Weekdays)
    09:00 am to 12:00 pm
  • Fees
    ₹50000 + GST
  • Trainer
    8+ years of industry level rich experience
  • Tool
  • Mode of Training
  • Certificate
  • Rating

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